1. Field of the Invention
This invention relates generally to floating gate semiconductor memory devices such as EEPROMs. More specifically, this invention relates to methods of manufacturing floating gate semiconductor memory devices such as EEPROMs. Even more specifically, this invention relates to methods of manufacturing floating gate semiconductor memory devices such as EEPROMs that reduce the amount of gate-edge lifting.
2. Discussion of the Related Art
A class of non-volatile memory devices known as xe2x80x9cflashxe2x80x9d EEPROM (Electrically Erasable Programmable Read Only Memory) devices combines the advantages of EPROM density with the electrical erasability of an EEPROM. One feature that distinguishes flash EEPROM memory cells from standard EEPROM memory cells is that unlike standard EEPROM memory cells, flash EEPROM memory cells do not contain a select transistor on a one-for-one basis with each floating gate memory cell. A select transistor is a transistor that allows the selection of an individual memory cell within the memory device and is used to selectively erase a specific memory cell. Because flash EEPROMs do not have a select transistor for each floating gate transistor, flash EEPROM memory cells cannot be individually erased and therefore must be erased in bulk, either by erasing the entire chip or by erasing paged groups or banks of cells. Elimination of the select transistor allows for smaller cell size and gives the flash EEPROM an advantage in terms of manufacturing yield (in terms of memory capacity) over comparably sized standard EEPROMs.
Typically, a plurality of flash EEPROM cells is formed on a semiconductor substrate, which is also known as a silicon wafer. FIG. 1 illustrates a single conventional flash EEPROM memory cell having a double-diffused source region. As shown in FIG. 1, flash memory cell 100 is formed on a p-type substrate 110 and includes an n type double-diffused source region 102 and an n+drain region 104. The drain region 104 and the source region 102 are spaced apart from each other forming a channel region 122. A source electrode 114 and a drain electrode 112 are connected to the source region 102 and the drain region 104, respectively.
The double-diffused source region 102 is formed of a lightly doped n region 128 (phosphorous doped) and a more heavily doped but shallower n+region 130 (arsenic doped) embedded within the deep n region 128. The phosphorus doping within n region 128 reduces the horizontal electric field between the source region 102 and the substrate 110.
The floating gate 106 is disposed a short distance above the source region 102, the drain region 104 and the channel region 122 over a dielectric layer 118, which is also known as a tunnel oxide region. Above the floating gate 106 and disposed over the dielectric layer 116 is a control gate 108. The dielectric layer 116 is typically formed of an oxide/nitride/oxide layer known in the semiconductor manufacturing art as an ONO layer. A control gate electrode 120 is attached to control gate 108. The dimension LGATE 132 represents the gate length for the gates contained in flash memory cell 100.
In a conventional method of operation, the programming of a flash EEPROM memory cell is achieved by inducing xe2x80x9chot electronxe2x80x9d injection from a section of the channel 122 near the drain 104 into the floating gate 106. The injected electrons cause the floating gate 106 to carry a negative charge. Grounding the source region 102, biasing the control gate 108 to a relatively high positive voltage and biasing the drain region 104 to a moderate positive voltage induce the hot electrons.
For example, to program the flash memory cell 100, the source electrode 114 is connected to ground, the drain electrode 112 is connected to a relatively high voltage (typically +4 volts to +9 volts) and the control gate electrode 120 is connected to a relatively high voltage level (typically +8 volts to +12 volts). Electrons are accelerated from source region 102 to drain region 104 via the channel 122 via the channel 122 and the xe2x80x9chot electronsxe2x80x9d are generated near the drain region 104. Some of the hot electrons are injected through the relatively thin gate dielectric layer 118 and become trapped in the floating gate 106 thereby giving floating gate 106 a negatively potential.
After sufficient negative charge accumulates on floating gate 106, the negative potential of floating gate 106 raises the threshold voltage of the stacked gate transistor and inhibits current flow through the channel 122 during a subsequent xe2x80x9creadxe2x80x9d mode. The magnitude of the read current is used to determine whether a memory cell has been programmed.
Conversely, to erase a flash memory device, electrons are typically driven out of the floating gate 106 by biasing the control gate 108 to a large negative voltage and biasing the source region 102 to a low positive voltage in order to produce a sufficiently large vertical electric field in the tunnel oxide. The large vertical field 136 in the tunnel oxide produces Fowler-Nordheim (F-N) tunneling of electrons stored in the floating gate 106 through the tunnel oxide into the source region 102. Arrows 105 indicate the tunneling of the electrons from the floating gate 106 to the source region 102. The charge removed from the floating gate 106 produces a threshold voltage shift.
For example, during erasure a relatively low positive voltage (typically from +0.5 volts to +5 volts) is applied to source electrode 114 and a relatively large negative voltage (typically from xe2x88x927 volts to xe2x88x9213 volts) is applied to control gate electrode 120. The voltage of the substrate electrode 126 is grounded and the drain electrode 112 is allowed to float. The vertical electric field established between the control gate 108 and the source region 102 induces electrons previously stored in floating gate 106 to pass through dielectric layer 118 and into source region 102 by way of Fowler-Nordheim tunneling.
In order to produce a sufficient electric field in the tunnel oxide, it is typically necessary to bias the control gate 108 to a large enough negative voltage such that the floating gate 106 reaches a voltage of approximately xe2x88x925.5 volts. A typical potential difference VSF between the source region 102 and floating gate 106 is on the order of 10 volts and accordingly, when the source voltage VS is made less positive, the control gate voltage VCG should be made more negative. Once the source to floating voltage VSF is selected, the remaining factors are preferably constrained according to the equation:
VFG=xcex1CG(VCGxe2x88x92xcex94VT) +xcex1SVS+xcex1BVB
where:
VFG=the floating gate voltage;
VCG=the control gate voltage;
Vs=the source voltage;
VB=the substrate or p-well bias;
xcex94VT=the threshold voltage difference arising from negative charge added to the floating gate as measured from the control gate;
xcex1CG=the capacitive coupling coefficient from the control gate to the floating gate;
xcex1S=the capacitive coupling coefficient between the source and the floating gate;
xcex1B=the capacitive coupling coefficient between the substrate or p-well and the floating gate.
As technology advances, a continuing goal throughout the industry is to increase the density of memory devices. By reducing the size of a flash EEPROM device a greater memory capacity can be achieved. As can be appreciated, the more die per wafer, the cost per die can be reduced. In addition, using higher density memory devices may provide for a reduction in the overall power consumption.
In order to increase the memory density of flash EEPROM devices, the memory cells are typically scaled down in size, for example the reduction in overall footprint of the device, is accomplished by reducing the gate length (LGATE) 132. However, a problem with reducing the length of the memory cell gates is that the distance LCHANNEL 122 between the source region 102 and the drain region 104 must also be reduced. As the source region 102 approaches the drain region 104, the lateral diffusion from the phosphorous in the source region 128 causes a leakage between the source region 102 and the drain region 104 resulting in detrimental short channel effects. Short channel effects produce serious problems in the flash memory cells and are typically evident when the gate length (LGATE) 132 is reduced below 0.4 microns.
One method for reducing the short-channel effect would be to eliminate the double-diffused phosphorous region 128. By using a single-diffused source region, the phosphorous diffusion overlap distance LDD 124 would no longer present and the short channel effect problem would be significantly reduced. Eliminating the phosphorous diffusion overlap distance LDD 124 would allow for a gate length (LGATE) reduction below 0.4 microns and would provide for an increased packing density of the memory cells.
However, eliminating the phosphorous doped N region 128 produces the unwanted side effect of increasing the horizontal electric field EH in the pn junction between the source region 102 and the substrate 110 during erasure of the memory cell. This increase in the horizontal electric field EH contributes to an increase in the band-to-band current since it is generally accepted that:
Jbxe2x88x92txe2x88x92b=Abxe2x88x92txe2x88x92bf(E)exe2x88x92(Bbxe2x88x92txe2x88x92b/E)
where:
Jbxe2x88x92txe2x88x92b=band-to-band current density (amps/cm2)
Abxe2x88x92txe2x88x92b,Bbxe2x88x92txe2x88x92b=constants
f(E) sometimes modeled as E2 
E=SQRT (EV2+EH2) (the tunneling field in the junction).
Because of the source-to-substrate biasing during the erasure of the memory cell device, a reversed-biased pn junction is formed that produces band-to-band currents (also known as Zener currents) in the source junction. The band-to-band currents are normally several orders of magnitude larger than the Fowler-Nordheim current. This band-to-band current is hard to sustain from a circuit design point of view and is also believed to generate detrimental reliability problems such as hole trapping in the tunnel oxide.
One barrier to further decrease the size of flash memory cells is that during manufacture of the flash memory cells, there is a phenomenon called gate-edge lifting that occurs during an oxidation procedure. Gate-edge lifting causes the tunnel oxide to thicken at each end and is a particular problem at the source end of the tunnel oxide through which the electrons must tunnel during Fowler-Nordheim erasure. Because the gate-edge lifting is not the same for each memory cell, the erase characteristics of each memory cell may differ and as a result the erase procedure has to be extended to ensure that all memory cells are erased. In addition, in order for each memory cell to be erased at the lowest possible voltage the source region has to be extended under the gate region until the heavily doped region of the double diffused source region reaches a region under the tunnel oxide that has not been thickened. This helps improve the uniformity of cell erase characteristics. However, the extension of the source region under the gate until the heavily doped region reaches a non-thickened portion under the tunnel region prevents the memory cell from being shortened.
Therefore, what is needed is a method of manufacturing flash memory cells that decreases the amount of gate-edge lifting so that the distance the source needs to extend under the gate is decreased allowing the memory cell to be shortened.
According to the present invention, the foregoing and other objects and advantages are achieved by a method of manufacturing a flash memory cell with a predetermined amount of gate edge lifting.
In an aspect of the invention, a gate stack is formed on a substrate wherein the gate stack comprises a layer of tunnel oxide, a floating gate, a layer of ONO and a control gate. The ends of the layer of tunnel oxide are etched forming cavities between the substrate and floating gate at the ends of the layer of tunnel oxide. A layer of oxide is deposited and anisotropically etched to form spacers on the sides of the gate stack wherein the cavities are also filled with the deposited oxide. The spacers have a predetermined thickness that controls the amount of gate edge lifting.
In another aspect of the invention, the predetermined thickness is determined during a characterization procedure.
In another aspect of the invention, the characterization procedure is determined either by computer modeling procedure and an empirical method.
In another aspect of the invention, phosphorus and arsenic ions are implanted into the substrate to form a double diffused source region and a drain region.
In another aspect of the invention, a second anneal process drives the implanted phosphorus and arsenic ions into the substrate.
In another aspect of the invention, as second anneal process drives the implanted phosphorus and arsenic ions into the substrate.
The described method of manufacturing a flash memory cell thus provides a flash memory cell with a predetermined amount of gate edge lifting.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.